1. Field of the Invention
Embodiments of the invention relate to a delay circuit used in storage media. More particularly, embodiments of the invention relate to a broadband multi-phase output delay locked loop circuit including a delay matrix.
2. Discussion of Related Art
Due to the growth of the semiconductor industry and material engineering, optical storage media have been developed to store high-capacity data. Currently, CD and DVD technology comprise the standardized form of optical storage media and can store 650 MB and 4.7 GB of data respectively. Next generation storage media such as, for example, a Blu-ray disc, uses a laser having a wavelength of 405 nm to store data with a capacity of approximately 25 GB in similarly sized CDs. The Blu-ray disc has the largest capacity among currently existing optical storage media and can read and write data with a minimum speed of 66 Mb/s. Accordingly, circuits which perform high speed read/write operations to such discs are also required. Different data input/output speeds depend on the position radius of the disc when data is read from the disc. In addition, consistent read/write operation must be supported in all frequency domains making the use of a broadband delay locked loop (DLL) circuit essential. In a typical 12×-speed blue-ray disc, the disc band remarkably broadens and the frequency domain required by the DLL circuit is 60 MHz to 800 MHz. Existing DLL circuit designs do not accommodate this frequency domain. In addition, the clock signals utilized by the DLL circuit must accommodate 40 different phases to generate signals for the write operation across all frequencies.
A restriction on generating the various phases at high-speeds is the relatively small delay margin. When generating N phases which are separated by the same delay, a delay margin should be T/N for a clock cycle T and an error between the delays should be smaller than T/2N. For example, if 20 phases are generated in a 12×-speed blue-ray disc, the highest frequency is set at 792 MHz and an error between the delays should be smaller than 31 ps. However, generating a plurality of phases restricts high-speed circuit operation. In other words, when N phases are generated, the number of delay stages should be N or N/2 at a minimum. Accordingly, the maximum locking frequency depends on the number of delay stages.